1,System Design
In the question of the receiver design,signal reception for the 70 MHz IF,10 MHz bandwidth OFDM signal.Unlike traditional receiver structure on the 70 MHz IF frequency analog signals then proceed to the practice of sampling in the structure of the receiver PDR,the direct IF sampling,the sampling frequency is 80 MHz,then sampling the signal and digital downconversion four times the filter taken by M Baud rate of 20 baseband signal sent to the DSP,FPGA part demodulator.Drop aimed at reducing the rate of DSP and FPGA computing load.Circuit structure as shown in Figure 1.
2 GCl012B and configuration
Since Graychip company (now acquired by TI) introduced the world's first digital downconversion ASIC,which many companies have developed a Digital Downconversion chips,there are relatively well-known Harris (1999,it has changed its name to Intersil),ADI and Stanford Telecom,etc..
The figures used in the circuit of the inverter is Graychip GCl012B.GCl012B 3.3 V power supply CMOS devices,the maximum input signal sampling rate of 100 MHz,50 MHz bandwidth.GCl012B not compatible with 5 V level,will not be allowed between 5 V,the signal directly from any of its pins,otherwise,they will damage devices.NC modules including internal oscillator,digital mixer,variable rate from low-pass filter,variable gain amplifier,data formats,such as choice of modules.Microprocessor interface through the internal registers to configure the chip can be changed working conditions.Its structure as shown in Figure 2.
The chip is 120-pin QFP packages,in the 3.3 V power supply,70 MHz signal input of about 900 mW of power.The dynamic range of over 75 dB,0.1 Hz frequency resolution,gain adjustment step is 0.03 dB.Chip output modes are real,complex two options.Set to real mode,I only port in the output data set to multiple mode,the output I,Q quadrature data from two directions.Input data width is 12,the output data width is 16.
GCl012B work in the state of internal registers from the controlled vocabulary identified.Power system,the microcontroller can be used with GCl012B microprocessor interface configurations.Tuning frequency / from 28-bit FREQ by (1) shall be determined,which fs for the input signal sampling frequency.
In this system,the sampling frequency is 80 MHz,tuning frequency of 10 MHz,so FREQ:(2000000) HEX.GCl012B SS # signal synchronization in accordance with the data and status word to the baseband frequency,and overturned four times from the spectrum to the plural form of output I and Q data from two directions. 1,System Design
In the question of the receiver design,signal reception for the 70 MHz IF,10 MHz bandwidth OFDM signal.Unlike traditional receiver structure on the 70 MHz IF frequency analog signals then proceed to the practice of sampling in the structure of the receiver PDR,the direct IF sampling,the sampling frequency is 80 MHz,then sampling the signal and digital downconversion four times the filter taken by M Baud rate of 20 baseband signal sent to the DSP,FPGA part demodulator.Drop aimed at reducing the rate of DSP and FPGA computing load.Circuit structure as shown in Figure 1.
2 GCl012B and configuration
Since Graychip company (now acquired by TI) introduced the world's first digital downconversion ASIC,which many companies have developed a Digital Downconversion chips,there are relatively well-known Harris (1999,it has changed its name to Intersil),ADI and Stanford Telecom,etc..
The figures used in the circuit of the inverter is Graychip GCl012B.GCl012B 3.3 V power supply CMOS devices,the maximum input signal sampling rate of 100 MHz,50 MHz bandwidth.GCl012B not compatible with 5 V level,will not be allowed between 5 V,the signal directly from any of its pins,otherwise,they will damage devices.NC modules including internal oscillator,digital mixer,variable rate from low-pass filter,variable gain amplifier,data formats,such as choice of modules.Microprocessor interface through the internal registers to configure the chip can be changed working conditions.Its structure as shown in Figure 2.
The chip is 120-pin QFP packages,in the 3.3 V power supply,70 MHz signal input of about 900 mW of power.The dynamic range of over 75 dB,0.1 Hz frequency resolution,gain adjustment step is 0.03 dB.Chip output modes are real,complex two options.Set to real mode,I only port in the output data set to multiple mode,the output I,Q quadrature data from two directions.Input data width is 12,the output data width is 16.
GCl012B work in the state of internal registers from the controlled vocabulary identified.Power system,the microcontroller can be used with GCl012B microprocessor interface configurations.Tuning frequency / from 28-bit FREQ by (1) shall be determined,which fs for the input signal sampling frequency.
In this system,the sampling frequency is 80 MHz,tuning frequency of 10 MHz,so FREQ:(2000000) HEX.GCl012B SS # signal synchronization in accordance with the data and status word to the baseband frequency,and overturned four times from the spectrum to the plural form of output I and Q data from two directions.